The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly relates to a technique effectively applied to a semiconductor device including a fin field effect transistor.
A fin field effect transistor is known as a field effect transistor that operates at high speed, and allows a reduction in leakage current, power consumption, and size. The fin field effect transistor (FINFET) is, for example, a semiconductor element that has a channel layer including a pattern of a plate-like (wall-like) semiconductor layer protruding above a substrate, and has a gate electrode formed so as to straddle the pattern.
Japanese Unexamined Patent Publication No. Hei01(1989)-82672 describes that a metal oxide semiconductor field effect transistor (MOSFET) has a plurality of trenches in a main surface, in which a channel is formed, of a semiconductor substrate to expand an effective channel width.
Japanese Unexamined Patent Publication No. 2012-49286 describes that ion implantation is performed to a fin in an oblique direction, thereby the same amount of an impurity is introduced into a side surface portion and an upper planar portion of the fin.
In general, a semiconductor device is required to be reduced in size and improved in degree of integration, and a fin field effect transistor is now the subject of interest as one structure to meet such requirements. A low resistance FET configuring a logic circuit or an FET configuring a flash memory can be formed on a fin. On the other hand, a large current must be applied to a high-withstand-voltage MOSFET used in a circuit, which generates a high voltage applied for write and erase of a flash memory, and the like. Thus, it is difficult to provide a high-withstand-voltage fin MOSFET having a structure similar to that of a low-withstand-voltage transistor.
Specifically, although the low resistance FET and the FET configuring the flash memory can be reduced in size by using the fin structure, the high-withstand-voltage FET is less likely to be reduced in size, which hinders a reduction in size of a semiconductor device.
Other objects and novel features will be clarified from the description of this specification and the accompanying drawings.
A typical one of embodiments disclosed in the present application is briefly summarized as follows.
A semiconductor device of one embodiment includes a low-withstand-voltage transistor provided on a fin, and a high-withstand-voltage transistor having a channel including respective surfaces of a plurality of other fins and a top of a semiconductor substrate between the fins.
A method of manufacturing a semiconductor device according to one embodiment is to form a low-withstand-voltage transistor provided on a fin, and form a high-withstand-voltage transistor having a channel including respective surfaces of a plurality of other fins and atop of a semiconductor substrate between the fins.
According to one embodiment disclosed in the present application, performance of a semiconductor device can be improved.